A Soft Processor Overlay with Tightly-coupled FPGA Accelerator

Abstract

FPGA overlays are commonly implemented as coarse-grained reconfigurable architectures with a goal to improve designers’ productivity through balancing flexibility and ease of configuration of the underlying fabric. To truly facilitate full application acceleration, it is often necessary to also include a highly efficient processor that integrates and collaborates with the accelerators while maintaining the benefits of being implemented within the same overlay framework.

Publication
2nd International Workshop on Overlay Architectures for FPGAs (OLAF 2016
Ho-Cheung Ng
Ho-Cheung Ng
M.Phil, PhD Candidate (ICL)
Cheng Liu
Cheng Liu
PhD
Hayden Kwok-Hay So
Hayden Kwok-Hay So
Associate Professor