Latest

• PACoGen: A Hardware Posit Arithmetic Core Generator
• Design of quadruple precision multiplier architectures with SIMD single and double precision support
• Architecture Generator for Type-3 Unum Posit Adder/Subtractor
• Universal number posit arithmetic generator on FPGA
• An Unified Architecture for Single, Double, Double-Extended, and Quadruple Precision Division
• High-throughput cellular imaging with high-speed asymmetric-detection time-stretch optical microscopy under FPGA platform
• Area-Efficient Architecture for Dual-Mode Double Precision Floating Point Division
• Real-time object detection and classification for high-speed asymmetric-detection time-stretch optical microscopy on FPGA
• Configurable Architectures for Multi-Mode Floating Point Adders