Publications

(2020). FTDL: A tailored FPGA-overlay for deep learning with high scalability. DAC'20 (to appear).

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(2020). CSB-RNN: A faster-than-realtime RNN acceleration framework with compressed structured blocks. ICS'20 (to appear).

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(2020). Dynamic Sparse Training: Find Efficient Sparse Network From Scratch With Trainable Masked Layers. ICLR'20.

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(2020). FTDL: An FPGA-tailored architecture for deep learning systems. FPGA'20.

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(2020). A super real-time RNN framework with compressed structured block. BARC'20.

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(2019). E-LSTM: Efficient inference of sparse LSTM on embedded heterogeneous system. DAC'19.

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(2019). PACoGen: A Hardware Posit Arithmetic Core Generator. IEEE Access.

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(2019). A real-time coprime line scan super-resolution system for ultra-fast microscopy. TBioCAS.

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(2018). Large-scale multi-class image-based cell classification with deep learning. IEEE Journal of Biomedical and Health Informatics.

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(2018). Architecture Generator for Type-3 Unum Posit Adder/Subtractor. ISCAS'18.

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(2018). Universal number posit arithmetic generator on FPGA. DATE'18.

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(2017). Ultra-low latency continuous block-parallel stream windowing using FPGA on-chip memory. FPT'17.

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(2017). Image super-resolution for ultrafast optical time-stretch imaging. ICO-24.

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(2017). A parameterizable activation function generator for FPGA-based neural network applications. FCCM'17.

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(2017). All-passive pixel super-resolution of time-stretch imaging. Scientific Reports.

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(2017). High-throughput cellular imaging with high-speed asymmetric-detection time-stretch optical microscopy under FPGA platform. RECONFIG'16.

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(2016). High-throughput time-stretch imaging flow cytometry for multi-class classification of phytoplankton. Optics Express.

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(2016). Real-time object detection and classification for high-speed asymmetric-detection time-stretch optical microscopy on FPGA. FPT'16.

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(2016). Towards FPGA-assisted Spark: An SVM training acceleartion case study. RECONFIG'16.

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(2016). A Soft Processor Overlay with Tightly-coupled FPGA Accelerator. OLAF'16.

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(2016). Vertex-centric Graph Processing on FPGA. FCCM'16.

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(2015). Automatic Nested Loop Acceleration on FPGAs Using Soft CGRA Overlay. FSP'15.

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(2015). Configurable Architectures for Multi-Mode Floating Point Adders. TCSI'15.

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(2009). Operation scheduling for FPGA-based reconfigurable computers. FPL'09.

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